In 2014, Cypress unveiled the HyperBus interface which, by taking advantage of legacy features of parallel and serial interface memory, improves system performance, simplifies design, and allows for significant cost reductions. Among the solutions supporting HyperBus is HyperRAM, a new technology solution capable of achieving throughput of up to 333 MB/s, increased to 400 MB/s in HyperRAM 2.0. HyperRAM 2.0 is a high-speed, low-number, self-updating dynamic RAM (DRAM) designed for high-performance embedded systems that require memory expansion, such as automotive, industrial, consumer, and Internet of Things applications. HyperRAM 2.0 provides HyperBus and Octal SPI interfaces and provides read/write bandwidth of up to 400Mbps in DDR mode. HyperRAM By cooperating with Cypress, Winbond Electronics has already launched products with a density of 32MB to 512MB. Currently, 24BGA (6 x 8mm2) products are available with the Automotive Class and WLCSP (Chip Level Chip Scale Package) targeting the wearable consumer market and KGD (Known Good Die). Besides Cypress, other leading related MCU manufacturers such as NXP, Renesas, ST, and TI have already developed microcontrollers that support the HyperBus interface, and are also expected to support them in the future. At the same time, leading silicon IP providers such as Cadence, Synopsys, and Mobiveil have begun providing an IP for HyperBus memory control, thus accelerating the time to launch of products incorporating this memory solution. The main benefits of HyperRAM, which can greatly improve the performance of peripherals, are the following: Low power consumption: This advantage is achieved by Hybrid Sleep Mode (HSM) which draws only 45µ[email protected] and 55µW@3V (compared to @2000µW@ 3.3V of SDRAM in standby at the same capacity) Reduced space: The lower pin count allows to save valuable space on the PCB. Besides higher power consumption, low power SDRAM has a larger form factor than HyperRAM, and this does not make it an ideal solution when the footprint and PCB area are reduced as much as possible. As shown in Figure 1, the HyperRAM interface requires only 13 pins (DQ[7:0]and RWDS, CS#, RESET#, CK, CK#), which greatly simplifies PCB design and package size. Conversely, a conventional SDRAM solution requires 38 threads and 8 x 8 mm2 space in the 54BGA package, while the LP SDRAM solution requires 41 threads and 9 x 8 mm2 space in the 54BGA package. During the product design phase, more rivets will be available to implement additional features, making the solution more cost effective as well. Figure 1: Winbond HyperRAM block diagram Another related feature of HyperRAM is that it is self-refreshing RAM, which means that it can automatically return to standby after the read/write process is completed. This allows for less effort in system design and firmware development. In terms of use cases and industries that can benefit from this solution, they include all applications that require low power consumption and high computing power MCU such as automotive, Industry 4.0, smart home, wearable devices, and IoT devices. Moreover, for battery powered devices such as smart speakers and smart meters, low power consumption is essential for longer battery life. Winbond HyperRAM is an ideal solution for embedded AI and image processing for classification, as the device should be as small as possible, with enough memory space to support computing-intensive algorithms, such as face recognition, object detection, real-time image recognition and edge computing. “In terms of the real HyperRAM application state, there are two main streams: one is accurate image recognition, the other is voice recognition, and both support AI models for sound or image,” said Jackie Tsing, director of DRAM marketing at Winbond, in an interview. with EEWeb. SpiStack SpiStack is a memory solution developed by Winbond, which is formed by stacking a NOR die and a NAND die in the same package, for example, a 64MB serial NOR with a 1GB QspiNAND template. This solution gives designers the flexibility to store code in a NOR template and data in a NAND template. By stacking monolithic or heterogeneous flash units, SpiStack provides a wide range of memories with different densities of code and data storage, while providing maximum storage flexibility for designers to their design requirements. SpiStack 8 memories only require signal pins, no matter how many templates are stacked. The active template can be switched with a simple software template selection command, which provides a factory custom template ID number. The device can operate at up to 104MHz, which corresponds to a clock rate of 416MHz according to the Quad-SPI feature. Moreover, SpiStack (NOR + NAND) supports synchronous operation, which means that one template can be programmed or erased while the other can be programmed/scanned/read at the same time and vice versa. For example, an application can use a NOR die (SpiFlash, which provides better endurance and retention, and fast random access time) to store boot code and application code, while many high-volume data (such as learning data for built-in AI and camera images) on NAND template (QspiNAND). Several SpiFlash templates, each with a density of 16MB to 2GB, can be stacked with any combination of NOR and NAND templates. As shown in Figure 2, SpiStack provides better reading performance than serial NAND with continuous reading. This is because SpiStack supports synchronous operation: while a read operation is performed on one die, a write/erase operation can be performed on another, without interrupting the code execution of data updates. Figure 2: SpiStack vs. Serial NAND w/ Continue reading performance The main benefits arising from adopting a SpiStack solution are essentially three: Small PCB footprint: This is a mandatory requirement for many applications, including IoT, wearable, consumer, and medical devices Cost efficiency: The solution allows SpiStack reduces both the number of components and the number of pins, simplifying PCB layout and routing High flexibility: The size of NOR and NAND templates can be combined to meet specific application requirements. SpiFlash NOR flash is available in 16MB, 32MB, 64MB, 128MB and 256MB sizes, while QspiNAND is available in 512MB, 1GB and 2GB sizes. “The first benefit of our solution is that it can provide a smaller form factor, which is critical for applications such as the Internet of Things. The second is the cost, which can be reduced by assembling two memory dies in the same chipset,” said Wilson Huang, Marketing Director of the company. Winbond, the third advantage is for customers, who can choose any available density of NOR and NAND.Moreover, manufacturing costs can be reduced by combining two chips into one package, and hardware compatibility is maintained with the standard package, which is WSON 8mm x package 6mm 8-pad (See Figure 3) Figure 3: SpiStack WSON Package “We provide high quality products because we use only mature and reliable technologies (46nm NAND, 58nm NOR). So, the quality is very good and our customers do not need to care about the quality,” concluded the speakers from Winbond.
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