Exploring the early design of the RISC-V platform for performance and power consumption


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Written by Deepak Shankar, founder and CEO of Mirabilis Design, and Ranjith KR, Senior Application Architect at ELC Labs Pvt. Ltd. The RISC-V instruction set architecture is intended to increase software reusability across different applications and platforms. The modern system-on-chip (SoC) platform contains dozens of instruction set structures to meet market demands. These include applications, graphics, imaging, DSP radio, audio, security, power management, and special instruction set processors. The RISC-V open source instruction architecture provides a free and open instruction architecture that can meet most of these requirements. To design complex architectures, a system-wide modeling platform with a comprehensive library of buses, memories, and IP terminal blocks is required. This environment must simulate and analyze the non-functional requirements of power, timing, scheduling, and functionality. Modern SoCs have variations that run at different clock speeds and a set of hardware accelerators. The complexity of these SoCs makes it imprecise to test using analytical methods and impractical to validate using Verilog/VHDL. Solutions using programming languages ​​require significant effort in developing all the required IP blocks and then integrating them into the platform. Using the instruction set emulator can help early software development. But the models are too abstract to provide a realistic view of the system’s operation. The discrete event graphic simulator is a great solution for exploring and validating RISC-V SoC architectures. VisualSim Architect from Mirabilis Design is a software package that provides a large library of ready-made components that can be used to assemble system models. These include DDR3/4/5, LPDDR, Ethernet, RapidIO, PCIe, FiberChannel, Cache, DMA, AMBA, NoC, and 40 other technologies. Tools like VisualSim are used to simulate SoCs and systems in high-performance computing, multimedia, avionics, automotive, networking, and the Internet of Things. Once the models are compiled in VisualSim, the designer can experiment with hardware software partitioning, program task scheduling, architecture selection, resource allocation, and power management. Using simulation models, the proposed architecture will be measured, analyzed and regression tested quantitatively rather than guesswork and hints from previous designs. The generated model is simulated using a wide variety of use cases, workloads, body combinations, peripherals, I/Os, memories, and DMA. Multi-core RISC-V will be deployed with network topology and NoC for different target activities. The lack of a consistent set of applications early in the design stage makes performance difficult to predict. In the case of VisualSim, the program can be simulated with either instruction sequences or delay values. They are generated based on profile statistics. Exploring an architecture for a monitoring SoC using the VisualSim Architect RISC-V architecture In this paper, we consider a high-performance computing design using a 16-core RISC-V architecture. To study this architecture, we use the VisualSim hybrid pipeline model of the RISC-V kernel, with out-of-order behavior, cache, instruction set, and execution units. User can select any configuration for iCache, dCache, L2 (external or internal), cross bar, optional L3, and external memory. The model can be simulated by sending various sequences of instructions to check the performance of the candidate architecture. Model parameters can be modified to specify the correct memory structure to keep the pipeline busy. The cache/memory size and configuration will be tested for bottlenecks while trying to prefetch instructions or data. The VisualSim sample will determine the system stop statistics for the processor block. The model was constructed at the system level with two clusters of eight parameterized cores with multiple clusters across NoC to study performance improvement with different core configurations. A major consideration in modern SoC architecture is significant energy savings. The proposed RISC-V platform will showcase a comprehensive energy system, starting with generation, storage (battery), consumption and management. The energy impact of a variety of management algorithms, routing tables, wireless channels, and battery types will be studied. The most important aspect of using system-wide design is the ability to see external activity from/to the processor and, if necessary, optimize external hardware accelerators, memory channels, bus topology, display, speed, etc. The designer gets insight into the processor and power performance combination of many known and unknown user applications. System-wide behavior analysis assesses performance, strength, and functional health. The combination of the three criteria of analysis is essential in making any architecture decision and provides insight into the entire system process. The main focus areas for exploration and analysis at the system level are: New designs: Designing a new platform requires exploring an architecture in terms of lower price, higher performance, and minimal power consumption. If the early assumptions prove incorrect during implementation, there will be a significant delay in the project schedule. For example, a dual RISC-V design is created and the bus is too slow or the memory hierarchy needs to be modified, which leads to a significant slowdown in video delivery. We’ll look at a recent design we developed in-house to compare dual RISC-V with the topology of the ARM Cortex M4 processor. Adding new apps to an existing platform: System companies want to add new apps using software on an existing hardware platform. When a new application is proposed, a simulation model is used to assess whether the existing platform will support rapid overhead. Based on this study, the designer can determine which parts of the application require a hardware accelerator. Early design exploration of performance, power and functionality provides validation of a new innovative design concept. Furthermore, the same infrastructure for system-level validation and marketing collateral can be used to achieve design victories. Assessment of the efficiency of the RISC-V core processor Memory latency sensor for high-throughput video data Software task latency on the RISC-V core Conclusion RISC-V has the potential to become a major disruptive technology in a variety of industries ranging from high-performance computing to the Internet of Things. . System-level models such as those in VisualSim Architect for RISC-V will enable designers to quickly define the configuration for their target application. Comprehensive IP address modeling will enable each type of SoC and system to be built and tested in the target application. These experiments can help create a SoC that can meet and exceed timing requirements, consume the least power, and meet the cost factor. .


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