I2C Bus Multiplexer


0

In this article, we will show how to build a two-way bidirectional circuit that can be used with I2C lines. The circuit also has the additional functionality of acting as a level switcher, if needed. The design is based on the GreenPAK™ SLG46826V. Due to the bidirectionality of the SDA and SCL lines, this design can be used for single-master or multiple I2C connections. This circuit is a two-bus integrated circuit that includes all the elements needed to create a two-way multiplexer circuit suitable for the I2C protocol. The use of this IC allows for a small form factor. In addition to the already small size of an I2C multiplexer circuit implementation, the GreenPAK is also capable of incorporating the necessary oscillator and pullup resistors for the circuit. The design is optimized for a real application and can be easily modified to suit the reader’s system requirements. It is checked by placing it within an I2C network consisting of an Arduino board and four I2C-LCD displays, where each display has the same I2C address. Each screen was individually written with the help of the designed IC. I2C protocol The connection of two or more devices to send and receive information requires a special communication path, which is controlled by a communication protocol common to both the sender and receiver. The integrated circuit bus, also known as I2C, is a very popular bidirectional communication bus, which uses two lines to send serial information between devices. I2C is used to create a network between a controller and a group of peripheral devices. It has become powered by many sensors and electronic actuators because it is efficient and easy to steer. The I2C bus supports a 7-bit and 10-bit address space device and consists of two signal lines: SCL and SDA lines, which are used to communicate with devices. SCL stands for “Serial Clock” which bears the master’s driven clock signal. SDA stands for Serial Data, in which the master and slave can send and receive data. When there is no transfer between I2C peripherals, both the SCL and SDA lines are pulled to the VDD. We can connect up to 128 devices using the I2C protocol, and they all share the same SCL and SDA lines. A small-scale example is shown in Figure 1. Systems often require several different supply voltages for various integrated circuits, and peripheral devices today are often linked to the microcontroller with the help of an I2C bus and an I2C level converter or an I2C bus multiplexer to solve the compatibility problem. Figure 1: I2C Network Diagram I2C Bus Multiplexer In I2C networks, each device must have a unique non-recursive address to properly achieve master-slave communication, but when multiple sensors and peripherals are combined on the same bus, the same I2C address can be assigned to more than one device. To solve this problem, we implement a unique multiplexing circuit that connects slaves with the same address to communication buses, and we can exchange channels through polling inputs. The I2C transmission multiplier circuit is a bi-directional selector for both SCL and SDA buses, and was designed using the SLG46826 dual-bus integrated circuits to build a four-channel output circuit as shown in Figure 2. SCL line bidirectionality, although not required For a single master system, it ensures that the topology can be used in a multi-master configuration, where the primary master (attached to the left side of Figure 2) can arbitrate whether the secondary master (connected to the address on the right-hand side of Figure 2) can send commands to the I2C network Main. Figure 2: I2C Bus Multiplexer IC GreenPAK Design Scheme The design consists of two main parts; SDA line multiplexer and SCL line multiplexer. The main behavior of this circuit is the configuration and flexibility of the SLG46826’s bidirectional pins and the OE (output enable) logic that configures whether a particular pin should be an input or an output. The complete design file created in GreenPAK Designer can be found on the Dialog website. SDA Line Multiplexer In this part Pin 3 will be connected to one of pins 7, 13, 15 and 16 depending on the state of the inputs A0 and A1. This input is configured to act as a digital input/output. The output type is Open Drain NMOS and the inputs are pulled up to 10k ohm resistors. As shown in Figure 3, NOR gates control the OE “output enable” of each pin; When OE is ‘low’, the pin becomes input connected to a 10K pull-up resistor, and when OE is ‘high’, the pin becomes output and is GND. Figure 3: SDA Line Mux design A 3-bit LUT7 output is connected to the OE of Pin 3 while the output of the 3L8 NOR gate is multiplexed and connected to the OE of pins 7, 13, 15, 16. Time delay blocks are configured to act as the falling edge delay and thus generate Time delay for NOR gates The 2-bit demultiplexer is built using blocks 3L3, 3L4, 3L5, 2L2, and 2L3. and so when [A1A0] = [00] Output 3L8 passes to Pin 7 and the active channel 0 to 3L3, while the rest of the channels are pulled to 1. When [A1A0] = [01] Output 3L8 passes to Pin 13 to 3L4, when [A1A0] = [10] The output passes to Pin 15 to 3L5, and when [A1A0] = [11] Output 3L8 passes to Pin 16 through gates AND 2L3 and 2L2. Figure 4: Characteristics of Pin 6 The 3L0, 3L1, and 3L2 squares were used to create a two-bit multiplier circuit; Then it selects one input signal coming from pins 7, 13, 15, 16 and passes it to the NOR gate to be later passed to Pin 3 (SDA). Pins 4 and 5 are configured to act as inputs associated with a pull-down resistor, then channel 0 is active [A0A1] = [00] in the initial case. MF1 and MF2 are multifunctional blocks that can be configured to perform more than one function. They were employed in this design to create a time delay, as well as forge a NOR gate. The “DLY IN” input of each counter is connected to the output of the NOR gate. Figure 5: The MF1 (Multifunctional Mass) configuration design sequence of events When the bus is idle (not sending or receiving), the contact pins are then connected to a pull-up (high) resistor and all the pins are in the input state according to the signal passing to the OE. If an input receives a LO signal, the signal is propagated through the NOR gate, causing an HI signal at the appropriate OE, based on A0A1. This creates the pin at the output and thus is held at GND. If the input returns to HI, a short OE state retention time delay is generated to account for the time the pin needs to change from LO to HI (input to output). To continue the sequence of events, consider this example: In the initial state, there is no communication on the bus, and [A1A0] = [00]. For example, all pins are inputs, and since the pull-up resistor is active to the input, the HI signal passes to the IC from all inputs. When Pin 3 receives LO from master, signal goes to 3L8, then to 3-bit LUT3 and 3L3 output is also low for the low signal up to OE of Pin 7 causing Pin 7 to change its state from input to output. The LO signal propagates to the external device through the SDA0 bus. When the master releases the contact bus, the input becomes high due to the current pulling resistance. Then the HI passes to the 3L8 which reflects the signal and passes the low signal to the OE of Pin 7, causing the pin to change its state from output to input. Since the pull-up resistor is active, HI is passed to the external device and a time delay is applied to the falling edge to give the pin enough time to change its I/O state before receiving new values. SCL line multiplexer Like the design of the SDA bus multiplier circuit, another SCL bus multiplier circuit is designed with the same configuration, with pins 6, 17, 18, 19 and 20 configured to act as the digital input/output energized and the internal pull-up resistor on the pins. Thus, the signal coming from the master via Pin 6 will be connected to one of the pins 17, 18, 19 and 20 according to A1 and A0. Blocks 3L11, 3L12, 3L13, and 2L0 were used to build a 2-bit demultiplexer while blocks 4L0, 3L6, and 2L1 were used to build 2-bit mux and thus bidirectional communication. Figure 6: SCL Line Mux Design Table 1: Selection of Input States The SLG46826 has dual VDD and VDD2 power supplies, which allows the design to add level shifting as another feature of the mux circuit. Pins 3, 6 and 7 are powered from VDD, while pins 13, 15, 16, 17, 18, 19 and 20 are powered from VDD2. Therefore, it is possible to use the mux circuit as a level switching circuit for channels 1, 2 and 3 without channel 0. The required voltage (VDD and VDD2) can be determined from the project information. Level change feature table 2: GreenPAK pins map of the implemented multiplier results to make sure the design works as expected, the design was put into a real-world scenario: to control four monitors (I2C-LCD) that all have the same fixed I2C address. All connections came from one master, in this case, the Arduino board. A program has been written for the Arduino board to act as a master and print a different statement on each screen through the I2C protocol. The displays on the buses were switched by an I2C mux circuit and Arduino digital outputs to control A0 and A1. Buses between screens were doubled before each print instruction. Figure 7 shows the screen output after execution. Figure 7: I2C-LCDs output after implementation by Dialog Semiconductor.


Like it? Share with your friends!

0

What's Your Reaction?

hate hate
0
hate
confused confused
0
confused
fail fail
0
fail
fun fun
0
fun
geeky geeky
0
geeky
love love
0
love
lol lol
0
lol
omg omg
0
omg
win win
0
win
Joseph

0 Comments

Your email address will not be published. Required fields are marked *